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Researcher, Virginia Polytechnic Institute and State University

1 Oct 201730 Sep 2019

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Dive into the research topics where Freek Verbeek is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
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  • Highly Automated Formal Proofs over Memory Usage of Assembly Code

    Verbeek, F., Bockenek, J. & Ravindran, B., 2020, Tools and Algorithms for the Construction and Analysis of Systems: 26th International Conference, TACAS 2020, Held as Part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2020, Dublin, Ireland, April 25–30, 2020, Proceedings, Part II. Biere, A. & Parker, D. (eds.). Cham: Springer Open, p. 98-117 20 p. (Lecture Notes in Computer Science (LNCS) series, Vol. 12079).

    Research output: Chapter in Book/Report/Conference proceedingConference Article in proceedingAcademicpeer-review

    Open Access
  • Sound C Code Decompilation for a Subset of x86-64 Binaries

    Verbeek, F., Olivier, P. & Ravindran, B., 2020, Software Engineering and Formal Methods: 18th International Conference, SEFM 2020, Amsterdam, The Netherlands, September 14–18, 2020, Proceedings. de Boer, F. & Cerone, A. (eds.). Cham: Springer Nature Switzerland AG, p. 247-264 18 p. (Lecture Notes in Computer Science (LNCS) series, Vol. 12310). (Theoretical Computer Science and General Issues (LNCS subseries), Vol. 12310).

    Research output: Chapter in Book/Report/Conference proceedingConference Article in proceedingAcademicpeer-review

  • A Compositional Approach for Verifying Protocols Running on On-Chip Networks

    Verbeek, F., Yaghini, P. M., Eghbal, A. & Bagherzadeh, N., Jul 2018, In: Ieee Transactions on Computers. 67, 7, p. 905-919 15 p.

    Research output: Contribution to journalArticleAcademicpeer-review

  • Deadlock Verification of Cache Coherence Protocols and Communication Fabrics

    Verbeek, F., Yaghini, P. M., Eghbal, A. & Bagherzadeh, N., Feb 2017, In: Ieee Transactions on Computers. 66, 2, p. 272-284 13 p.

    Research output: Contribution to journalArticleAcademicpeer-review

    2 Citations (Web of Science)
  • Estimating worst-case latency of on-chip interconnects with formal simulation

    Verbeek, F. & van Vugt - Hage, N., 2017, Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design (FMCAD 2017): TU Wien, Vienna, Austria, October 2-6, 2017. Stewart, D. & Weissenbacher, G. (eds.). IEEE, p. 204-211 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference Article in proceedingAcademicpeer-review