20172018
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Research Output 2017 2018

  • 2 Article
  • 1 Conference article in proceeding
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Conference article in proceeding
2017

Estimating worst-case latency of on-chip interconnects with formal simulation

Verbeek, F. & van Vugt - Hage, N., 2017, Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design (FMCAD 2017): TU Wien, Vienna, Austria, October 2-6, 2017. Stewart, D. & Weissenbacher, G. (eds.). IEEE, p. 204-211 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingAcademicpeer-review