Research output per year
Research output per year
Research output
- 1 Conference Article in proceeding
-
Estimating worst-case latency of on-chip interconnects with formal simulation
Verbeek, F. & van Vugt - Hage, N., 2017, Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design (FMCAD 2017): TU Wien, Vienna, Austria, October 2-6, 2017. Stewart, D. & Weissenbacher, G. (eds.). IEEE, p. 204-211 8 p.Research output: Chapter in Book/Report/Conference proceeding › Conference Article in proceeding › Academic › peer-review