Application of deterministic logic BIST on industrial circuits

G. Kiefer; H. Vranken; E.J. Marinissen; H.-J. Wunderlich

doi:10.1109/TEST.2000.894197

Application of deterministic logic BIST on industrial circuits

G. Kiefer, H. Vranken, E.J. Marinissen, H.-J. Wunderlich

Research output: Contribution to journal › Article › Academic › peer-review

Abstract

We present the application of a deterministic logic BIST scheme on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100 K gates with 10000 test patterns, at a total area cost for BIST hardware of typically 5%-15%. It is demonstrated that a tradeoff is possible between test quality, test time, and silicon area. In contrast to BIST schemes based on test point insertion no modifications of the circuit under test are required, complete fault efficiency is guaranteed, and the impact on the design process is minimized.

Original language	English
Journal	IEEE International Test Conference (TC)
DOIs	https://doi.org/10.1109/TEST.2000.894197
Publication status	Published - 2000
Externally published	Yes

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10.1109/TEST.2000.894197

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@article{9a3b4961517d4e6b9bd4a7d7bf1724dc,

title = "Application of deterministic logic BIST on industrial circuits",

abstract = "We present the application of a deterministic logic BIST scheme on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100 K gates with 10000 test patterns, at a total area cost for BIST hardware of typically 5%-15%. It is demonstrated that a tradeoff is possible between test quality, test time, and silicon area. In contrast to BIST schemes based on test point insertion no modifications of the circuit under test are required, complete fault efficiency is guaranteed, and the impact on the design process is minimized.",

author = "G. Kiefer and H. Vranken and E.J. Marinissen and H.-J. Wunderlich",

note = "http://www.scopus.com/inward/record.url?eid=2-s2.0-0034476155&partnerID=MN8TOARS",

year = "2000",

doi = "10.1109/TEST.2000.894197",

language = "English",

journal = "IEEE International Test Conference (TC)",

issn = "1089-3539",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - Application of deterministic logic BIST on industrial circuits

AU - Kiefer, G.

AU - Vranken, H.

AU - Marinissen, E.J.

AU - Wunderlich, H.-J.

N1 - http://www.scopus.com/inward/record.url?eid=2-s2.0-0034476155&partnerID=MN8TOARS

PY - 2000

Y1 - 2000

N2 - We present the application of a deterministic logic BIST scheme on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100 K gates with 10000 test patterns, at a total area cost for BIST hardware of typically 5%-15%. It is demonstrated that a tradeoff is possible between test quality, test time, and silicon area. In contrast to BIST schemes based on test point insertion no modifications of the circuit under test are required, complete fault efficiency is guaranteed, and the impact on the design process is minimized.

AB - We present the application of a deterministic logic BIST scheme on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100 K gates with 10000 test patterns, at a total area cost for BIST hardware of typically 5%-15%. It is demonstrated that a tradeoff is possible between test quality, test time, and silicon area. In contrast to BIST schemes based on test point insertion no modifications of the circuit under test are required, complete fault efficiency is guaranteed, and the impact on the design process is minimized.

U2 - 10.1109/TEST.2000.894197

DO - 10.1109/TEST.2000.894197

M3 - Article

SN - 1089-3539

JO - IEEE International Test Conference (TC)

JF - IEEE International Test Conference (TC)

ER -

Application of deterministic logic BIST on industrial circuits

Abstract

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