Application of deterministic logic BIST on industrial circuits

G. Kiefer, H. Vranken, E.J. Marinissen, H.-J. Wunderlich

Research output: Contribution to journalArticleAcademicpeer-review


We present the application of a deterministic logic BIST scheme on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100 K gates with 10000 test patterns, at a total area cost for BIST hardware of typically 5%-15%. It is demonstrated that a tradeoff is possible between test quality, test time, and silicon area. In contrast to BIST schemes based on test point insertion no modifications of the circuit under test are required, complete fault efficiency is guaranteed, and the impact on the design process is minimized.
Original languageEnglish
JournalIEEE International Test Conference (TC)
Publication statusPublished - 2000
Externally publishedYes


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