Debug facilities in the TriMedia CPU64 architecture

Research output: Contribution to journalArticleAcademicpeer-review


This paper describes debug facilities in the Philips TriMedia CPU64, which is an embedded processor core for multimedia applications. Its architecture provides a VLIW pipeline, support for 64-bit vector data, and virtual memory management. The debug hardware in the TriMedia CPU64 supports two complementary debug strategies. One strategy provides a snapshot of the processor state at certain moments in time, which is achieved by single-step execution and various breakpoint types. The other debug strategy provides continuous monitoring of the processor state by using a PC trace buffer. Precise exceptions are used to provide accurate context switching from application software to debugger software.
Original languageEnglish
Pages (from-to)301–308
JournalJournal of Electronic Testing: Theory and Applications
Publication statusPublished - 2000
Externally publishedYes


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