TY - GEN
T1 - Efficient pattern mapping for deterministic logic BIST
AU - Gherman, V.
AU - Wunderlich, H.-J.
AU - Vranken, H.
AU - Hapke, F.
AU - Wittke, M.
AU - Garbers, M.
PY - 2004
Y1 - 2004
N2 - Deterministic logic BIST (DLBIST) is an attractive test strategy, since it combines advantages of deterministic external testing and pseudo-random LBIST. Unfortunately, previously published DLBIST methods are unsuited for large ICs, since computing time and memory consumption of the DLBIST synthesis algorithms increase exponentially, or at least cubically, with the circuit size. In this paper, we propose a novel DLBIST synthesis procedure that has nearly linear complexity in terms of both computing time and memory consumption. The new algorithms are based on binary decision diagrams (BDDs). We demonstrate the efficiency of the new algorithms for industrial designs up to 2M gates.
AB - Deterministic logic BIST (DLBIST) is an attractive test strategy, since it combines advantages of deterministic external testing and pseudo-random LBIST. Unfortunately, previously published DLBIST methods are unsuited for large ICs, since computing time and memory consumption of the DLBIST synthesis algorithms increase exponentially, or at least cubically, with the circuit size. In this paper, we propose a novel DLBIST synthesis procedure that has nearly linear complexity in terms of both computing time and memory consumption. The new algorithms are based on binary decision diagrams (BDDs). We demonstrate the efficiency of the new algorithms for industrial designs up to 2M gates.
U2 - 10.1109/TEST.2004.1386936
DO - 10.1109/TEST.2004.1386936
M3 - Conference Article in proceeding
SN - 0-7803-8580-2
SP - 48
EP - 56
BT - Proceedings - International Test Conference
ER -