Enhanced reduced pin-count test for full-scan design

H. Vranken, T. Waayers, H. Fleury, D. Lelouvier

Research output: Contribution to journalArticleAcademicpeer-review


This paper presents enhanced reduced pin-count test (E-RPCT) for low-cost test. E-RPCT is an extension of traditional RPCT for circuits in which a large number of digital IC pins is multiplexed for scan. The basic concept of E-RPCT is to provide access to the internal scan chains via an IEEE 1149.1 compatible boundary-scan architecture, instead of direct access via the IC pins. The boundary-scan chain performs serial/parallel conversion of test data. E-RPCT also provides I/O wrap to test non-contacted pins. The paper presents E-PPCT for full-scan design, as well as for full-scan core-based design.
Original languageEnglish
Pages (from-to)738-747
JournalIEEE International Test Conference (TC)
Publication statusPublished - 2001
Externally publishedYes


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