Enhanced reduced pin-count test for full-scan design

H. Vranken; T. Waayers; H. Fleury; D. Lelouvier

doi:10.1109/TEST.2001.966695

Enhanced reduced pin-count test for full-scan design

H. Vranken, T. Waayers, H. Fleury, D. Lelouvier

Research output: Contribution to journal › Article › Academic › peer-review

Abstract

This paper presents enhanced reduced pin-count test (E-RPCT) for low-cost test. E-RPCT is an extension of traditional RPCT for circuits in which a large number of digital IC pins is multiplexed for scan. The basic concept of E-RPCT is to provide access to the internal scan chains via an IEEE 1149.1 compatible boundary-scan architecture, instead of direct access via the IC pins. The boundary-scan chain performs serial/parallel conversion of test data. E-RPCT also provides I/O wrap to test non-contacted pins. The paper presents E-PPCT for full-scan design, as well as for full-scan core-based design.

Original language	English
Pages (from-to)	738-747
Journal	IEEE International Test Conference (TC)
DOIs	https://doi.org/10.1109/TEST.2001.966695
Publication status	Published - 2001
Externally published	Yes

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abstract = "This paper presents enhanced reduced pin-count test (E-RPCT) for low-cost test. E-RPCT is an extension of traditional RPCT for circuits in which a large number of digital IC pins is multiplexed for scan. The basic concept of E-RPCT is to provide access to the internal scan chains via an IEEE 1149.1 compatible boundary-scan architecture, instead of direct access via the IC pins. The boundary-scan chain performs serial/parallel conversion of test data. E-RPCT also provides I/O wrap to test non-contacted pins. The paper presents E-PPCT for full-scan design, as well as for full-scan core-based design.",

author = "H. Vranken and T. Waayers and H. Fleury and D. Lelouvier",

year = "2001",

doi = "10.1109/TEST.2001.966695",

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AU - Waayers, T.

AU - Fleury, H.

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AB - This paper presents enhanced reduced pin-count test (E-RPCT) for low-cost test. E-RPCT is an extension of traditional RPCT for circuits in which a large number of digital IC pins is multiplexed for scan. The basic concept of E-RPCT is to provide access to the internal scan chains via an IEEE 1149.1 compatible boundary-scan architecture, instead of direct access via the IC pins. The boundary-scan chain performs serial/parallel conversion of test data. E-RPCT also provides I/O wrap to test non-contacted pins. The paper presents E-PPCT for full-scan design, as well as for full-scan core-based design.

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DO - 10.1109/TEST.2001.966695

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EP - 747

JO - IEEE International Test Conference (TC)

JF - IEEE International Test Conference (TC)

ER -

Enhanced reduced pin-count test for full-scan design

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