Estimating worst-case latency of on-chip interconnects with formal simulation

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingAcademicpeer-review

Original languageEnglish
Title of host publicationProceedings of the 17th Conference on Formal Methods in Computer-Aided Design (FMCAD 2017)
Subtitle of host publicationTU Wien, Vienna, Austria, October 2-6, 2017
EditorsDaryl Stewart, Georg Weissenbacher
PublisherIEEE
Pages204-211
Number of pages8
ISBN (Print)9780983567875
DOIs
Publication statusPublished - 2017

Cite this

Verbeek, F., & van Vugt - Hage, N. (2017). Estimating worst-case latency of on-chip interconnects with formal simulation. In D. Stewart, & G. Weissenbacher (Eds.), Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design (FMCAD 2017): TU Wien, Vienna, Austria, October 2-6, 2017 (pp. 204-211). IEEE. https://doi.org/10.23919/FMCAD.2017.8102261