Estimating worst-case latency of on-chip interconnects with formal simulation

Research output: Chapter in Book/Report/Conference proceeding › Conference Article in proceeding › Academic › peer-review

Original language	English
Title of host publication	Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design (FMCAD 2017)
Subtitle of host publication	TU Wien, Vienna, Austria, October 2-6, 2017
Editors	Daryl Stewart, Georg Weissenbacher
Publisher	IEEE
Pages	204-211
Number of pages	8
ISBN (Print)	9780983567875
DOIs	https://doi.org/10.23919/FMCAD.2017.8102261
Publication status	Published - 2017

Access to Document

@inproceedings{9ee24d858dfa46cb8f2fd6dc7d70b917,

title = "Estimating worst-case latency of on-chip interconnects with formal simulation",

author = "Freek Verbeek and {van Vugt - Hage}, Nik{\`e}",

year = "2017",

doi = "10.23919/FMCAD.2017.8102261",

language = "English",

isbn = "9780983567875",

pages = "204--211",

editor = "Daryl Stewart and Georg Weissenbacher",

booktitle = "Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design (FMCAD 2017)",

publisher = "IEEE",

address = "United States",

}

Estimating worst-case latency of on-chip interconnects with formal simulation. / Verbeek, Freek ; van Vugt - Hage, Nikè.
Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design (FMCAD 2017): TU Wien, Vienna, Austria, October 2-6, 2017. ed. / Daryl Stewart; Georg Weissenbacher. IEEE, 2017. p. 204-211.

Research output: Chapter in Book/Report/Conference proceeding › Conference Article in proceeding › Academic › peer-review

TY - GEN

T1 - Estimating worst-case latency of on-chip interconnects with formal simulation

AU - Verbeek, Freek

AU - van Vugt - Hage, Nikè

PY - 2017

Y1 - 2017

U2 - 10.23919/FMCAD.2017.8102261

DO - 10.23919/FMCAD.2017.8102261

M3 - Conference Article in proceeding

SN - 9780983567875

SP - 204

EP - 211

BT - Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design (FMCAD 2017)

A2 - Stewart, Daryl

A2 - Weissenbacher, Georg

PB - IEEE

ER -