Estimating worst-case latency of on-chip interconnects with formal simulation

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingAcademicpeer-review

Original languageEnglish
Title of host publicationProceedings of the 17th Conference on Formal Methods in Computer-Aided Design (FMCAD 2017)
Subtitle of host publicationTU Wien, Vienna, Austria, October 2-6, 2017
EditorsDaryl Stewart, Georg Weissenbacher
PublisherIEEE
Pages204-211
Number of pages8
ISBN (Print)9780983567875
DOIs
Publication statusPublished - 2017

Cite this

Verbeek, F., & van Vugt - Hage, N. (2017). Estimating worst-case latency of on-chip interconnects with formal simulation. In D. Stewart, & G. Weissenbacher (Eds.), Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design (FMCAD 2017): TU Wien, Vienna, Austria, October 2-6, 2017 (pp. 204-211). IEEE. https://doi.org/10.23919/FMCAD.2017.8102261
Verbeek, Freek ; van Vugt - Hage, Nikè. / Estimating worst-case latency of on-chip interconnects with formal simulation. Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design (FMCAD 2017): TU Wien, Vienna, Austria, October 2-6, 2017. editor / Daryl Stewart ; Georg Weissenbacher. IEEE, 2017. pp. 204-211
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title = "Estimating worst-case latency of on-chip interconnects with formal simulation",
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Verbeek, F & van Vugt - Hage, N 2017, Estimating worst-case latency of on-chip interconnects with formal simulation. in D Stewart & G Weissenbacher (eds), Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design (FMCAD 2017): TU Wien, Vienna, Austria, October 2-6, 2017. IEEE, pp. 204-211. https://doi.org/10.23919/FMCAD.2017.8102261

Estimating worst-case latency of on-chip interconnects with formal simulation. / Verbeek, Freek; van Vugt - Hage, Nikè.

Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design (FMCAD 2017): TU Wien, Vienna, Austria, October 2-6, 2017. ed. / Daryl Stewart; Georg Weissenbacher. IEEE, 2017. p. 204-211.

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingAcademicpeer-review

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T1 - Estimating worst-case latency of on-chip interconnects with formal simulation

AU - Verbeek, Freek

AU - van Vugt - Hage, Nikè

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DO - 10.23919/FMCAD.2017.8102261

M3 - Conference article in proceeding

SN - 9780983567875

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BT - Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design (FMCAD 2017)

A2 - Stewart, Daryl

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Verbeek F, van Vugt - Hage N. Estimating worst-case latency of on-chip interconnects with formal simulation. In Stewart D, Weissenbacher G, editors, Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design (FMCAD 2017): TU Wien, Vienna, Austria, October 2-6, 2017. IEEE. 2017. p. 204-211 https://doi.org/10.23919/FMCAD.2017.8102261