@inproceedings{9ee24d858dfa46cb8f2fd6dc7d70b917,
title = "Estimating worst-case latency of on-chip interconnects with formal simulation",
author = "Freek Verbeek and \{van Vugt - Hage\}, Nik{\`e}",
year = "2017",
doi = "10.23919/FMCAD.2017.8102261",
language = "English",
isbn = "9780983567875",
pages = "204--211",
editor = "Daryl Stewart and Georg Weissenbacher",
booktitle = "Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design (FMCAD 2017)",
publisher = "IEEE",
address = "United States",
}