X-masking during logic BIST and Its impact on defect coverage

Y. Tang; H.-J. Wunderlich; H. Vranken; F. Hapke; M. Wittke; P. Engelke; I. Polian; B. Becker

doi:10.1109/TEST.2004.1386980

X-masking during logic BIST and Its impact on defect coverage

Y. Tang
, H.-J. Wunderlich
, H. Vranken
, F. Hapke
, M. Wittke
, P. Engelke
, I. Polian
, B. Becker

Research output: Chapter in Book/Report/Conference proceeding › Conference Article in proceeding › Academic › peer-review

Abstract

We present a technique for making a circuit ready for logic BIST by masking unknown values at its outputs. In order to keep the silicon area cost low, some known bits in output responses are also allowed to be masked. These bits are selected based on a stuck-at n-detection based metric, such that the impact of masking on the defect coverage is minimal. An analysis based on a probabilistic model for resistive short defects indicates that the coverage loss for unmodeled defects is negligible for relatively low values of n.

Original language	English
Title of host publication	Proceedings - International Test Conference
Pages	442-451
DOIs	https://doi.org/10.1109/TEST.2004.1386980
Publication status	Published - 2004
Externally published	Yes

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10.1109/TEST.2004.1386980

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title = "X-masking during logic BIST and Its impact on defect coverage",

abstract = "We present a technique for making a circuit ready for logic BIST by masking unknown values at its outputs. In order to keep the silicon area cost low, some known bits in output responses are also allowed to be masked. These bits are selected based on a stuck-at n-detection based metric, such that the impact of masking on the defect coverage is minimal. An analysis based on a probabilistic model for resistive short defects indicates that the coverage loss for unmodeled defects is negligible for relatively low values of n.",

author = "Y. Tang and H.-J. Wunderlich and H. Vranken and F. Hapke and M. Wittke and P. Engelke and I. Polian and B. Becker",

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language = "English",

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booktitle = "Proceedings - International Test Conference",

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AU - Tang, Y.

AU - Wunderlich, H.-J.

AU - Vranken, H.

AU - Hapke, F.

AU - Wittke, M.

AU - Engelke, P.

AU - Polian, I.

AU - Becker, B.

PY - 2004

Y1 - 2004

N2 - We present a technique for making a circuit ready for logic BIST by masking unknown values at its outputs. In order to keep the silicon area cost low, some known bits in output responses are also allowed to be masked. These bits are selected based on a stuck-at n-detection based metric, such that the impact of masking on the defect coverage is minimal. An analysis based on a probabilistic model for resistive short defects indicates that the coverage loss for unmodeled defects is negligible for relatively low values of n.

AB - We present a technique for making a circuit ready for logic BIST by masking unknown values at its outputs. In order to keep the silicon area cost low, some known bits in output responses are also allowed to be masked. These bits are selected based on a stuck-at n-detection based metric, such that the impact of masking on the defect coverage is minimal. An analysis based on a probabilistic model for resistive short defects indicates that the coverage loss for unmodeled defects is negligible for relatively low values of n.

U2 - 10.1109/TEST.2004.1386980

DO - 10.1109/TEST.2004.1386980

M3 - Conference Article in proceeding

SP - 442

EP - 451

BT - Proceedings - International Test Conference

ER -

X-masking during logic BIST and Its impact on defect coverage

Abstract

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