Yield analysis for repairable embedded memories

A. Sehgal, A. Dubey, E.J. Marinissen, C. Wouters, H. Vranken, K. Chakrabarty

Research output: Chapter in Book/Report/Conference proceedingConference Article in proceedingAcademicpeer-review


Repairable embedded memories help improve the overall yield of an IC. We have developed a yield analysis tool that provides realistic yield estimates for both single repairable memories, as well as for ICs containing multiple, possibly different, repairable embedded memories. Our approach uses pseudo-randomly generated fault bit-maps, which are based on memory area size, defect density, and fault distribution. In order to accommodate a wide range of industrial memory and redundancy organizations, we have developed a flexible memory model. It generalizes the traditional simple memory matrix model with partitioning into regions, grouping of columns and rows, and column-wise and row-wise coupling of the spares. Our tool is used to determine an optimal amount of spare columns and rows for a given memory, as well as to determine the effectiveness of various repair algorithms.
Original languageEnglish
Title of host publicationProceedings of the European Test Workshop
Publication statusPublished - 2003
Externally publishedYes


Dive into the research topics of 'Yield analysis for repairable embedded memories'. Together they form a unique fingerprint.

Cite this